November 30, 2024

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Samsung Electronics officials move 3-nanometer chip wafers to a shipping truck at the tech giant`s chip-making complex in Hwaseong, Gyeonggi Province, on Monday. (Yonhap)

Samsung Electronics has started shipping chips produced using the world’s most advanced 3-nanometer manufacturing technology, which has drastically improved power consumption and performance.

On Monday, the tech giant held a ceremony to celebrate the departure of the first batch of 3nm chips from its chip-making complex in Hwaseong, Gyeonggi Province, with some 100 company and government officials in attendance.

The 3nm technology is Samsung’s secret weapon to outpacing its rival TSMC. Despite its prowess in memory chips, Samsung remains a distant No. 2 in the burgeoning foundry market with less than 20 percent share, with TSMC dominating, with more than 50 percent of the global market.

Samsung’s 3nm technology boasts higher transistor density than the current 5nm technology, which means higher speed and lower power consumption of advanced chips for artificial intelligence, big data and autonomous cars.

Samsung is also the first chipmaker to adopt a more advanced transistor architecture, called gate-all-around field-effect transistor technology (GAAFET), which has increased the overall efficiency of the current fin field-effect transistor technology (FinFET).

Samsung trademarked its own GAAFET technology as “Multi-Bridge-Channel FET (MBCFET).”

GAAFET is considered essential for next-generation foundry microfabrication, which is smaller than 3nm, but chipmakers are struggling to elevate the low yield rate in the earlier production stage.

According to Samsung, its engineers started research work on the GAAFET technology in the early 2000s and adopted the technology for the then-upcoming 3nm manufacturing process in 2017. Last month, the company made the mass production of the 3nm chips official, becoming the first chipmaker to do so.

“The latest 3nm production is a milestone for Samsung’s foundry business,” Kyung Kye-hyun, CEO of Samsung’s chip business division, told researchers at the event. “At a time when the FinFET technology is nearing its limits, we have succeeded in developing the GAAFET technology as an alternative earlier than others. This is a result of innovation.”

As a result of overall technological upgrades, Samsung said its first-generation 3nm process has reduced power consumption by 45 percent and improved performance by 23 percent, compared to the current 5nm process using FinFET.

For the second generation, power consumption is expected to be cut in half, with performance being boosted by 30 percent.

Samsung is adopting the latest technology to chips for high-performance computing and plans to diversify the application in partnership with clients.

The company added that it is considering ramping up production to manufacture the chips at its other chip-making complex in Pyeongtaek, Gyeonggi Province.

By Lee Ji-yoon  (jylee@heraldcorp.com)